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mitsubishi storage card preliminary ata pc cards mitsubishi electric 1 june . 2001 rev. 1.3 8/16 - bit data bus flash ata pc card connector type two - piece 68 - pin mf00 32 m - 11 atxx mf0 064 m - 11 atxx mf0 128 m - 11 atxx mf0 192 m - 11 atxx mf0256m - 11atxx mf0320m - 11atxx mf0384m - 11atxx mf0448m - 11atxx mf0512m - 11atxx description mitsubishi?s flash ata cards provide large memory capacities on a device approximately the size of a credit card (85.6mm(l) 54mm(w) 3.3mm(t) or 5mm(t)). the cards use an 8/16 bit data bus. available in 32mb - 512 mb ca pacities, mitsubishi?s flash ata cards conform to the jeid a/pcmcia standard. in default mode, the ata card operates in pc card compliant sockets. it conforms to pcmcia 2.1,jeida 4.2 and pc card standard. when the oe# signal is asserted low level by the host system in power on cycle, the mitsubishi?s flash ata c ards can be selected in a ide ata interface. it uses the ata command set so no software drivers are required. features 68pin pc card standard type - i pc card single 5v or 3.3v supply card density of up to 512 mb maximum four pc card ata and ide ata modes nonvolatile, no batteries required high reliability based on internal ecc function fast read/write performance(target) read:1.5mb/s write:1.6mb/s(128 - 512mb) write:850kb/s(64mb) write:450kb/s(32mb) read:1.8m b/s write:1.7mb/s(128mb - 512mb) write:1.0mb/s(64mb) write:550kb/s(32mb) 300,000 program/erase cycles applications computers digital camera data communication office automation industrial consumer
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 2 june . 2001 rev. 1.3 product list memory capacity (bytes) dat a bus width(bits) memory cylinder head sector out line mf0032m - 11atxx 32,047,104 256mbit flash x 1 489 4 32 mf 0 064m - 11atxx 64,094,208 256mbit flash x 2 978 4 32 mf0128m - 11atxx 128,188,416 256mbit flash x 4 978 8 32 mf0192m - 11atxx 192,15 1,552 256mbit flash x 6 733 16 32 mf0256m - 11atxx 256,376,832 256mbit flash x 8 978 16 32 mf0320m - 11atxx 319,979,520 256mbit flash x 10 620 16 63 mf0384m - 11atxx 384,491,520 256mbit flash x 12 745 16 63 mf0448m - 11atxx 448,487,424 256mbit flash x 14 869 16 63 mf0512m - 11atxx 512,483,328 8/16 256mbit flash x 16 993 16 63 type i
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 3 june . 2001 rev. 1.3 pin assignment pc card memory mode pc card i/o mode ide ata interface pc card memory mode pc card i/o mode ide ata interface pin signal i/o signal i/o signal i/o pin signal i/o signal i/o signal i/o 1 gnd - gnd - gnd - 35 gnd - gnd - gnd - 2 d3 i/o d3 i/o d3 i/o 36 cd1# o cd1# o cd1# o 3 d4 i/o d4 i/o d4 i/o 37 d11 i/o d11 i/o d11 i/o 4 d5 i/o d5 i/o d5 i/o 38 d12 i/o d12 i/o d12 i/o 5 d6 i/o d6 i/o d6 i/o 39 d13 i/ o d13 i/o d13 i/o 6 d7 i/o d7 i/o d7 i/o 40 d14 i/o d14 i/o d14 i/o 7 ce1# i ce1# i cs0# i 41 d15 i/o d15 i/o d15 i/o 8 a10 i a10 i n.u - 42 ce2# i ce2# i cs1# i 9 oe# i oe# i ata sel# i 43 vs1# o vs1# o vs1# o 10 n.c - n.c - n.c - 44 n.u - iord# i iord# i 11 a9 i a9 i n.u - 45 n.u - iowr# i iowr# i 12 a8 i a8 i n.u - 46 n.c - n.c - n.c - 13 n.c - n.c - n.c - 47 n.c - n.c - n.c - 14 n.c - n.c - n.c - 48 n.c - n.c - n.c - 15 we# i we# i we# i 49 n.c - n.c - n.c - 16 ready o ireq# o intrq o 50 n.c - n.c - n.c - 17 vcc - vcc - vcc - 51 vcc - vcc - vcc - 18 n.c - n.c - n.c - 52 n.c - n.c - n.c - 19 n.c - n.c - n.c - 53 n.c - n.c - n.c - 20 n.c - n.c - n.c - 54 n.c - n.c - n.c - 21 n.c - n.c - n.c - 55 n.c - n.c - n.c - 22 a7 i a7 i n.u - 56 csel i csel i csel i 23 a6 i a6 i n.u - 57 vs2# o vs2# o vs2# o 24 a5 i a5 i n.u - 58 reset i reset i reset# i 25 a4 i a4 i n.u - 59 wait# o wait# o iordy o 26 a3 i a3 i n.u - 60 n.u - inpack# o inpack# o 27 a2 i a2 i a2 i 61 reg# i reg# i reg# i 28 a1 i a1 i a1 i 62 bvd2 o spkr# o dasp# i/o 29 a0 i a0 i a0 i 63 bvd1 o stschg# o pdiag# i/o 30 d0 i/o d0 i/o d0 i/o 64 d8 i/o d8 i/o d8 i/o 31 d1 i/o d1 i/o d1 i/o 65 d9 i/o d9 i/o d9 i/o 32 d2 i/o d2 i/o d2 i/o 66 d10 i/o d10 i/ o d10 i/o 33 wp o iois16# o iocs16# o 67 cd2# o cd2# o cd2# o 34 gnd - gnd - gnd - 68 gnd - gnd - gnd - n.c = not connected internally. n.u = not used.
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 4 june . 2001 rev. 1.3 signal description signal name i/o pin no. description address bus[a10 - a0] i 8, 11, 12, 22, 23, 2 4, 25, 26, 27, 28, 29 signals a10 - a0 are address bus. a0 is invalid in word mode. a10 is the msb and a0 is the lsb. data bus[d15 - d0] i/o 41, 40, 39, 38, 37, 66, 65, 64, 6, 5, 4, 3, 2 ,32,31, 30 signals d15 - d0 are data bus. d0 is the lsb of the even byte o f the word. d8 is the lsb of the odd byte of the word. card enable[ce1#, ce2#] (pc card memory mode) card enable[ce1#, ce2#] (pc card i/o mode) ce1# and ce2# are low active card select signals. chip select[cs0#, cs1#] (ide ata interface) i 7, 42 in ide ata interface, cs0# is used to select the command block registers. cs1# is used to select the control block registers. output enable[oe#] (pc card memory mode) oe# is used to gate attribute and common memory read data from the ata card. output enable[oe#] (pc card i/o mode) oe# is used to gate attribute memory read data from the ata card. ata sel# (ide ata interface) i 9 to enable ide ata interface, this input should be grounded by the host. write enable[we#] (pc card memory mode) we# is used for strobing attribute and common memory write data into the ata card. write enable[we#] (pc card i/o mode) we# is used for strobing attribute memory write data into the ata card. write enable[we#] (ide ata interface) i 15 this input should be conne cted vcc by the host. i/o read[iord#] (pc card i/o mode) i/o read[iord#] (ide ata interface) i 44 iord# is used to read data from the card?s i/o space. i/o write[iowr#] (pc card i/o mode) i/o write[iowr#] (ide ata interface) i 45 iowr# is used to write data to the card?s i/o space. ready[ready] (pc card memory mode) ready signal is set high when the ata card is ready to accept a new data transfer operation. ireq# (pc card i/o mode) this signal of low level is indicates that the card is re questing software service to host, and high level indicates that the card is not requesting. intrq (ide ata interface) o 16 this signal is active high interrupt request to the host. card detection[cd1#, cd2#] o 36, 67 cd1# and cd2# provided for proper detec tion of pc card insertion. write protect[wp] (pc card memory mode) this signal is held low because this card does not have a write protect switch. iois16# (pc card i/o mode) iocs16# (ide ata interface) o 33 this output signal is asserted when the i/o port address is capable of 16 - bit access.
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 5 june . 2001 rev. 1.3 signal description(continued) signal name i/o pin no. description attribute memory select[reg#] (pc card memory mode) attribute memory select[reg#] (pc card i/o mode) when this signal is asserted, access is limited to attribute memory with oe#/we# and i/o space with iord#/iowr#. attribute memory select[reg#] (ide ata interface) i 61 this input signal is not used for this mode and should be connected to vcc by the host. battery voltage detect[bvd2] (pc card memory mode) this output is driven to a high - level. audio digital waveform[spkr#] (pc card i/o mode) o spkr# is kept negated because this card does not have digital audio output. dasp# (ide ata interface) i/o 62 this signal is the disk active/sl ave present signal in the master/slave handshake protocol. card reset[reset] (pc card memory mode) card reset[reset] (pc card i/o mode) by assertion of this signal, all registers of this card are cleared. this signal should be kept to high - z or high level by the host for at least 1ms af ter vcc applied. card reset[reset#] (ide ata interface) i 58 this input pin is the active low hardware reset from the host. wait[wait#] (pc card memory mode) wait[wait#] (pc card i/o mode) iordy (ide ata interface) o 59 this signal is asserted to delay completion of the me mory or i/o access cycle. input port acknowledge[inpack#] (pc card i/o mode) input port acknowledge[inpack#] (ide ata interface) o 60 this signal is asserted when the card is selected and can respond to an i/o read cycle at the address on the address bus. battery voltage detect[bvd1] (pc card memory mode) this output is driven to a high - level. stschg# (pc card i/o mode) o this signal is asserted low to alert the host to changes in the status of configuration status register in the attribute memory space. pdiag# (ide ata interface) i/o 63 this signal is the pass diagnostic signal in the master/slave handshake protocol. voltage sense[vs1, vs2] o 43, 57 vs1 is grounded so that the car d cis can be read at 3.3v and vs2 is n.c. cable select[csel] (pc card memory mode) - cable select[csel] (pc card i/o mode) - this signal is not used for this mode. cable select[csel] (ide ata interface) i 56 this signal is used to configure this card as a master or a slave. when this signal is grounded, this card is configured as a master. when this signal is open, this card is configure as a slave. vcc - 17, 51 5v or 3.3v power. gnd - 1, 34, 35, 68 ground.
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 6 june . 2001 rev. 1.3 block diagram vcc gnd a10 - a0 ce1#/cs0# ce2#/cs1# oe#/ata sel# we# iord# iowr# reg# reset/reset# d15 - d0 ready/ireq#/intrq wp/iois16#/iocs16# inpack# bvd1/stschg#/pdiag# bvd2/spkr#/dasp# wait#/iordy csel vs1 vs2 cd1# cd2# controller por# res# ce# oe# we# cde# sc i/o7 - i/o0 r/b# xin xout 64mbit and flash memory (x14) 256mbit and flash memory (x 16 : 512 mb) reset circuit open resonator internal vcc
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 7 june . 2001 rev. 1.3 function table function reg# ce2# ce1# a0 oe# we# iord# iowr# d15 - d8 d7 - d0 attribute memory read function standby x h h x x x x x high - z high - z l h l l l h h h high - z even byte byte access l h l h l h h h high - z invalid word access l l l x l h h h invalid even byte odd byte l l h x l h h h invalid high - z attribute memory write function standby x h h x x x x x don?t care don?t care l h l l h l h h don?t care even byte byte access l h l h h l h h don?t care don?t care word access l l l x h l h h don?t care even byte odd byte l l h x h l h h don?t care don?t care common memory read function standby x h h x x x x x high - z high - z h h l l l h h h high - z even byte byte access h h l h l h h h high - z odd byte word access h l l x l h h h o dd byte even byte odd byte h l h x l h h h odd byte high - z common memory write function standby x h h x x x x x don?t care don?t care h h l l h l h h don?t care even byte byte access h h l h h l h h don?t care odd byte word access h l l x h l h h od d byte even byte odd byte h l h x h l h h odd byte don?t care i/o read function standby x h h x x x x x high - z high - z l h l l h h l h high - z even byte byte access l h l h h h l h high - z odd byte word access l l l x h h l h odd byte even byte odd by te l l h x h h l h odd byte high - z i/o write function standby x h h x x x x x don?t care don?t care l h l l h h h l don?t care even byte byte access l h l h h h h l don?t care odd byte word access l l l x h h h l odd byte even byte odd byte l l h x h h h l odd byte don?t care
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 8 june . 2001 rev. 1.3 memory mapped mode(index=0) register reg# ce2# ce1# a10 a9 - a4 a3 a2 a1 a0 oe#=?l? we#=?l? 1 0 0 0 x 0 0 0 x data register(d15 - d0) data register(d15 - d0) 1 1 0 0 x 0 0 0 0 data register[even, odd](d7 - d0) data regist er[even, odd](d7 - d0) 1 1 0 0 x 0 0 0 1 error register(d7 - d0) feature register(d7 - d0) 1 0 1 0 x 0 0 0 x error register(d15 - d8) feature register(d15 - d8) 1 0 0 0 x 0 0 1 x sector count register(d7 - d0) sector number register(d15 - d8) sector count register(d7 - d0) sector number register(d15 - d8) 1 1 0 0 x 0 0 1 0 sector count register(d7 - d0) sector count register(d7 - d0) 1 1 0 0 x 0 0 1 1 sector number register(d7 - d0) sector number register(d7 - d0) 1 0 1 0 x 0 0 1 x sector number register(d15 - d8) sector number register(d15 - d8) 1 0 0 0 x 0 1 0 x cylinder low register(d7 - d0) cylinder high register(d15 - d8) cylinder low register(d7 - d0) cylinder high register(d15 - d8) 1 1 0 0 x 0 1 0 0 cylinder low register(d7 - d0) cylinder low register(d7 - d0) 1 1 0 0 x 0 1 0 1 cyli nder high register(d7 - d0) cylinder high register(d7 - d0) 1 0 1 0 x 0 1 0 x cylinder high register(d15 - d8) cylinder high register(d15 - d8) 1 0 0 0 x 0 1 1 x drive head register(d7 - d0) status register(d15 - d8) drive head register(d7 - d0) command register(d15 - d 8) 1 1 0 0 x 0 1 1 0 drive head register(d7 - d0) drive head register(d7 - d0) 1 1 0 0 x 0 1 1 1 status register(d7 - d0) command register(d7 - d0) 1 0 1 0 x 0 1 1 x status register(d15 - d8) command register(d15 - d8) 1 0 0 0 x 1 0 0 x data register(d15 - d0) data register(d15 - d0) 1 1 0 0 x 1 0 0 0 data register[even, odd](d7 - d0) data register[even, odd](d7 - d0) 1 1 0 0 x 1 0 0 1 data register[odd](d7 - d0) data register[odd](d7 - d0) 1 0 1 0 x 1 0 0 x data register[odd](d15 - d8) data register[odd](d15 - d8) 1 0 0 0 x 1 1 0 x invalid(d7 - d0) error register(d15 - d8) invalid(d7 - d0) feature register(d15 - d8) 1 1 0 0 x 1 1 0 0 invalid invalid 1 1 0 0 x 1 1 0 1 error register(d7 - d0) feature register(d7 - d0) 1 0 1 0 x 1 1 0 x error register(d15 - d8) feature register(d15 - d8) 1 0 0 0 x 1 1 1 x alt. status register(d7 - d0) drive address register(d15 - d8) device control register(d7 - d0) invalid 1 1 0 0 x 1 1 1 0 alt. status register(d7 - d0) device control register(d7 - d0) 1 1 0 0 x 1 1 1 1 drive address register(d7 - d0) invalid 1 0 1 0 x 1 1 1 x drive address register(d15 - d8) invalid 1 0 0 1 x x x x x data register(d15 - d0) data register(d15 - d0) 1 1 0 1 x x x x 0 data register[even, odd](d7 - d0) data register[even, odd](d7 - d0) 1 1 0 1 x x x x 1 data register[odd](d7 - d0) data register[o dd](d7 - d0) 1 0 1 1 x x x x x data register[odd](d15 - d8) data register[odd](d15 - d8)
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 9 june . 2001 rev. 1.3 contiguous i/o map(index=1) register reg# ce2# ce1# a9 - a4 a3 a2 a1 a0 iord#=?l? iowr#=?l? 0 0 0 x 0 0 0 x data register(d15 - d0) data register(d15 - d0) 0 1 0 x 0 0 0 0 data register[even, odd](d7 - d0) data register[even, odd](d7 - d0) 0 1 0 x 0 0 0 1 error register(d7 - d0) feature register(d7 - d0) 0 0 1 x 0 0 0 x error register(d15 - d8) feature register(d15 - d8) 0 0 0 x 0 0 1 x sector count register(d7 - d0) sector num ber register(d15 - d8) sector count register(d7 - d0) sector number register(d15 - d8) 0 1 0 x 0 0 1 0 sector count register(d7 - d0) sector count register(d7 - d0) 0 1 0 x 0 0 1 1 sector number register(d7 - d0) sector number register(d7 - d0) 0 0 1 x 0 0 1 x sector number register(d15 - d8) sector number register(d15 - d8) 0 0 0 x 0 1 0 x cylinder low register(d7 - d0) cylinder high register(d15 - d8) cylinder low register(d7 - d0) cylinder high register(d15 - d8) 0 1 0 x 0 1 0 0 cylinder low register(d7 - d0) cylinder low regi ster(d7 - d0) 0 1 0 x 0 1 0 1 cylinder high register(d7 - d0) cylinder high register(d7 - d0) 0 0 1 x 0 1 0 x cylinder high register(d15 - d8) cylinder high register(d15 - d8) 0 0 0 x 0 1 1 x drive head register(d7 - d0) status register(d15 - d8) drive head register( d7 - d0) command register(d15 - d8) 0 1 0 x 0 1 1 0 drive head register(d7 - d0) drive head register(d7 - d0) 0 1 0 x 0 1 1 1 status register(d7 - d0) command register(d7 - d0) 0 0 1 x 0 1 1 x status register(d15 - d8) command register(d15 - d8) 0 0 0 x 1 0 0 x data r egister(d15 - d0) data register(d15 - d0) 0 1 0 x 1 0 0 0 data register[even, odd](d7 - d0) data register[even, odd](d7 - d0) 0 1 0 x 1 0 0 1 data register[odd](d7 - d0) data register[odd](d7 - d0) 0 0 1 x 1 0 0 x data register[odd](d15 - d8) data register[odd](d15 - d 8) 0 0 0 x 1 1 0 x invalid(d7 - d0) error register(d15 - d8) invalid(d7 - d0) feature register(d15 - d8) 0 1 0 x 1 1 0 0 invalid invalid 0 1 0 x 1 1 0 1 error register(d7 - d0) feature register(d7 - d0) 0 0 1 x 1 1 0 x error register(d15 - d8) feature register(d15 - d 8) 0 0 0 x 1 1 1 x alt. status register(d7 - d0) drive address register(d15 - d8) device control register(d7 - d0) invalid 0 1 0 x 1 1 1 0 alt. status register(d7 - d0) device control register(d7 - d0) 0 1 0 x 1 1 1 1 drive address register(d7 - d0) invalid 0 0 1 x 1 1 1 x drive address register(d15 - d8) invalid
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 10 june . 2001 rev. 1.3 primary(secondary) i/o(index=2, 3) register reg# ce2# ce1# a9 - a4 a3 a2 a1 a0 iord#=?l? iowr#=?l? 0 0 0 1fh(17h) 0 0 0 x data register(d15 - d0) data register(d15 - d0) 0 1 0 1fh(17h) 0 0 0 0 data r egister[even, odd](d7 - d0) data register[even, odd](d7 - d0) 0 1 0 1fh(17h) 0 0 0 1 error register(d7 - d0) feature register(d7 - d0) 0 0 1 1fh(17h) 0 0 0 x error register(d15 - d8) feature register(d15 - d8) 0 0 0 1fh(17h) 0 0 1 x sector count register(d7 - d0) sec tor number register(d15 - d8) sector count register(d7 - d0) sector number register(d15 - d8) 0 1 0 1fh(17h) 0 0 1 0 sector count register(d7 - d0) sector count register(d7 - d0) 0 1 0 1fh(17h) 0 0 1 1 sector number register(d7 - d0) sector number register(d7 - d0) 0 0 1 1fh(17h) 0 0 1 x sector number register(d15 - d8) sector number register(d15 - d8) 0 0 0 1fh(17h) 0 1 0 x cylinder low register(d7 - d0) cylinder high register(d15 - d8) cylinder low register(d7 - d0) cylinder high register(d15 - d8) 0 1 0 1fh(17h) 0 1 0 0 cyli nder low register(d7 - d0) cylinder low register(d7 - d0) 0 1 0 1fh(17h) 0 1 0 1 cylinder high register(d7 - d0) cylinder high register(d7 - d0) 0 0 1 1fh(17h) 0 1 0 x cylinder high register(d15 - d8) cylinder high register(d15 - d8) 0 0 0 1fh(17h) 0 1 1 x drive he ad register(d7 - d0) status register(d15 - d8) drive head register(d7 - d0) command register(d15 - d8) 0 1 0 1fh(17h) 0 1 1 0 drive head register(d7 - d0) drive head register(d7 - d0) 0 1 0 1fh(17h) 0 1 1 1 status register(d7 - d0) command register(d7 - d0) 0 0 1 1fh(1 7h) 0 1 1 x status register(d15 - d8) command register(d15 - d8) 0 0 0 3fh(37h) 0 1 1 x alt. status register(d7 - d0) drive address register(d15 - d8) device control register(d7 - d0) invalid 0 1 0 3fh(37h) 0 1 1 0 alt. status register(d7 - d0) device control regist er(d7 - d0) 0 1 0 3fh(37h) 0 1 1 1 drive address register(d7 - d0) invalid 0 0 1 3fh(37h) 0 1 1 x drive address register(d15 - d8) invalid ide ata interface register cs1# cs0# a2 - a0 iord#=?l? iowr#=?l? 1 0 0h data register(d15 - d0) data register(d15 - d0) 1 0 1h error register(d7 - d0) feature register(d7 - d0) 1 0 2h sector count register(d7 - d0) sector count register(d7 - d0) 1 0 3h sector number register(d7 - d0) sector number register(d7 - d0) 1 0 4h cylinder low register(d7 - d0) cylinder low register(d7 - d0) 1 0 5h cylinder high register(d7 - d0) cylinder high register(d7 - d0) 1 0 6h drive head register(d7 - d0) drive head register(d7 - d0) 1 0 7h status register(d7 - d0) command register(d7 - d0) 0 1 6h alt. status register(d7 - d0) device control register(d7 - d0) 0 1 7h drive address register(d7 - d0) invalid
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 11 june . 2001 rev. 1.3 configuration register specifications configuration option register this register is used for the configuration of the card configuration status and for the issuing soft reset to the card. d7 d6 d5 d4 d3 d 2 d1 d0 sreset levireq index name r/w description sreset r/w setting this bit to ?1?, places the card in the reset state. when the host returns this bit to ?0?, the function shall enter the same unconfigured, reset state as the card does following a po wer - up and hardware reset. levireq r/w if this bit is set to ?0?, card generates pulse mode interrupt. if this bit is set to ?1?, card generates level mode interrupts. index r/w this bits is used for select operation mode of the card as follows. when pow er on, card hard reset and soft reset, this data is ?000000? for the purpose of memory card interface recognition. index: 0 - > memory mapped 1 - > contiguous i/o mapped 2 - > primary i/o mapped 3 - > second ary i/o mapped configuration and status register this register is used for observing the card state. d7 d6 d5 d4 d3 d2 d1 d0 changed sigchg iois8 0 0 pwrdwn intr 0 name r/w description changed r/o this bit indicates that cready bit on the pin replac ement register is set to ?1?. when changed bit is set to ?1?, stschg# pin is held ?l? if the sigchg bit is ?1? and the card is configured for the i/o interface. sigchg r/w this bit is set or reset by the host for enabling and disabling the status change signal(stschg# pin). when the card is configured i/o card interface and this bit is set to ?1?, stschg# pin is controlled by changed bit. if this bit is set to ?0?, stschg# pin is kept ?h?. iois8 r/w this card is always configured for both 8 - bit and 16 - bi t i/o, so this bit is ignored. pwrdwn r/w when this bit is set to ?1?, the card enters power down mode. when this bit is reset to ?0?, the host is requesting the card to enter the active mode. rready bit on pin replacement register becomes busy when this bit is changed. rready will not become ready until the power state requested has been entered. this card automatically powers down when it is idle, and powers back up when it receives a command. intr r/w this bit represents the internal state of the inter rupt request. this bit state is available whether i/o card interface has been configured or not. this signal remains true until the condition which caused the interrupt request has been serviced. if interrupts are disabled by the nien bit in the device con trol register, this bit is a zero. pin replacement register this register is used for providing the signal state of ready signal when the card configured i/o card interface. d7 d6 d5 d4 d3 d2 d1 d0 0 0 cready 0 1 1 rready 0 name r/w description crea dy r/w this bit is set to ?1? when the rready bit changes state. this bit may also be written by the host. rready r/w when read, this bit indicates ready pin states. when written, this bit acts as a mask for writing the cready bit. socket and copy regis ter this register is used for identification of the card from the other cards. host can read and write this register. this register should be set by host before this card?s configuration option register set. d7 d6 d5 d4 d3 d2 d1 d0 0 copy number socket n umber name r/w description copy number r/w this bit indicates the drive number of the card for twin card configuration. and the host can select and drive one card by comparing the number in this field with the drive number of drive head register. in the way, the host can perform the card?s master/slave organization. socket number r/w this field indicates to the card that it is located in the n?th socket.
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 12 june . 2001 rev. 1.3 cis information cis informatoins are defined as follows. offset data 7 6 5 4 3 2 1 0 description 0000h 01h cistpl_device common memory device information 0002h 03h tpl_link link to next tuple 0004h d9h device type wps device speed device type=dh : function specific wps=1 : no wps device speed=1 : 250ns 0006h 01h 1x 2k 2kbytes of add ress space 0008h ffh marks end of device info fields 000ah 1ch cistpl_device_oc other conditions device information 000ch 04h tpl_link link to next tuple 000eh 02h ext reserved vcc mwait ext=0, vcc=5.0v, wait is not used. 0010h d 9 h device type wps de vice speed device type=dh : function specific wps=1 : no wps device speed=250ns 0012h 01h 1x 2k 2kbytes of address space 0014h ffh marks end of other conditions device info 0016h 1ch cistpl_device_oc other conditions device information 0 018h 04h tpl_link link to next tuple 001ah 02h ext reserved vcc mwait ext=0, vcc=3.3v, wait is not used. 001ch d9h device type wps device speed device type=dh : function specific wps=1 : no wps device speed=250ns 001eh 01h 1x 2k 2kbytes of address space 0020h ffh marks end of other conditions device info 0022h 18h cistpl_jedec_c jedec identifier tuples 0024h 02h tpl_link link to next tuple 0026h dfh jedec identifier for first device info entry. pc card ata 0028h 01h jedec identifiers for remaining device info entries. with no vpp require for any operation 002ah 20h cistpl_manfid manufacturer identification tuple 002ch 04h tpl_link link to next tuple 002eh 1ch 0030h 00h pc card manufacturer code 001ch 0032h 01h 0034h 00h manufacturer infor mation 0001h 0036h 15h cistpl_vers_1 level 1 version / product information 0038h 1ch tpl_link link to next tuple 003ah 04h tpllv1_major pcmcia2.0 / jeida4.1 003ch 01h tpllv1_minor pcmcia2.0 / jeida4.1 003eh 4dh m 0040h 49h i 0042h 54h t 0044h 53h s 0046h 55h u 0048h 42h b 004ah 49h i 004ch 53h s 004eh 48h h 0050h 49h i 0052h 00h 0054h 41h a 0056h 54h t 0058h 41h a 005ah 20h 005ch 43h c 005eh 41h a 0060h 52h r 0062h 44h d 0064h 00h tpllv1_info
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 13 june . 2001 rev. 1.3 cis information(continued) offset data 7 6 5 4 3 2 1 0 description 0066h 34h 4 0068h 2eh . 006ah 30h 0 006ch 30h 0 006eh 00h 0070h ffh marks end of chain. 0072h 21h cistpl_funcid function identification tuple 0074h 02h tpl_link link to next tupl e 0076h 04h card function code pc card ata(fixed disk) 0078h 01h reserved rom post rom=0 : no bios rom post=1: configure card at power on 007ah 22h cistpl_funce function extension tuple 007ch 02h tpl_link link to next tuple 007eh 01h disk function ext ension tuple type disk interface type 0080h 01h disk interface type pc card ata interface 0082h 22h cistpl_funce function extension tuple 0084h 03h tpl_link link to next tuple 0086h 02h disk function extension tuple type basic pc card ata interface tup le 0088h 04h rfu d u s v v=0 : no vpp required s=1 : silicon u=0 : id drive mfg/sn not unique d=0 : single drive on card 008ah 0fh rfu i e n p3 p2 p1 p0 p0=1 : sleep mode supported p1=1 : standby mode supported p2=1 : idle mode supported p3=1 : drive aut o power control n=0 : no configs exclude i/o port 3f7h/377h e=0 : index bit is not emulated i=0 : iois16 # use is unspecified on twin card configurations 008ch 1ah cistpl_conf configuration tuple 008eh 05h tpl_link link to next tuple 0090h 01h rfs rms ras rfs=0 : no reserved field rms=0 : 1 byte register mask ras=1 : 2 byte config base address 0092h 03h tpcc_last last index = 3 0094h 00h tpcc_radr (lsb) configuration registers are located 0096h 02h tpcc_radr (msb) at 200h in reg sp ace 0098h 0fh rfu rfu rfu e s p c i first 4 configuration registers present 009ah 1bh cistpl_cftable_entry configuration table entry tuple 009ch 08h tpl_link link to next tuple 009eh c0h i d configuration index interface byte follows, default entry, co nfiguration index = 0 00a0h 40h w r p b interface type mem interface; bvd's and wprot not used; ready active and wait not used for memory cycles. 00a2h a1h m ms ir io t p has vcc, mem space and misc info 00a4h 01h r di pi ai si hv lv nv nominal voltage only follows 00a6h 55h x mantissa exponent vcc nominal is 5 volts 00a8h 08h length in 256 bytes pages (lsb) length of mem space is 2 kb 00aah 00h length in 256 bytes pages (msb) starts at 0 on card 00ach 21h x rfu p ro a t power down, twin card support ed. 00aeh 1bh cistpl_cftable_entry configuration table entry tuple 00b0h 05h tpl_link link to next tuple 00b2h 00h i d configuration index no interface byte, non default entry, configuration index = 0 00b4h 01h m ms ir io t p has vcc info 00b6h 01h r di pi ai si hv lv nv nominal voltage only follows 00b8h b5h x mantissa exponent vcc nominal is 3.3 volts 00bah 1eh extension
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 14 june . 2001 rev. 1.3 cis information(continued) offset data 7 6 5 4 3 2 1 0 description 00bch 1bh cistpl_cftable_entry configuration table entry t uple 00beh 0ah tpl_link link to next tuple 00c0h c1h i d configuration index interface byte follows, default entry, configuration index = 1 00c2h 41h w r p b interface type i/o interface; bvd's and wprot not used; ready active and wait not used for memo ry cycles. 00c4h 99h m ms ir io t p has vcc, i/o, irq and misc info 00c6h 01h r di pi ai si hv lv nv nominal voltage only follows 00c8h 55h x mantissa exponent vcc nominal is 5 volts 00cah 64h r s e io addrlines i/o : range=0, bus16=1, bus8=1, io addr lines=4 00cch f0h s p l m level or mask share=1, pulse=1, level=1, mask=1 00ceh ffh irq7 irq6 irq5 irq4 irq3 irq2 irq1 irq0 irq level to be routed 0 - 15 00d0h ffh irq15 irq14 irq13 irq12 irq11 irq10 irq9 irq8 recommended. 00d2h 21h x rfu p ro a t powe r down, twin card supported. 00d4h 1bh cistpl_cftable_entry configuration table entry tuple 00d6h 05h tpl_link link to next tuple 00d8h 01h i d configuration index no interface byte, non default entry, configuration index = 1 00dah 01h m ms ir io t p h as vcc info 00dch 01h r di pi ai si hv lv nv nominal voltage only follows 00deh b5h x mantissa exponent vcc nominal is 3.3 volts 00e0h 1eh extension 00e2h 1bh cistpl_cftable_entry configuration table entry tuple 00e4h 0fh tpl_link link to next tuple 00e6h c2h i d configuration index interface byte follows, default entry, configuration index = 2 00e8h 41h w r p b interface type i/o interface; bvd's and wprot not used; ready active and wait not used for memory cycles. 00eah 99h m ms ir io t p has vcc , i/o, irq and misc info 00ech 01h r di pi ai si hv lv nv nominal voltage only follows 00eeh 55h x mantissa exponent vcc nominal is 5 volts 00f0h eah r s e io addrlines i/o : range=1, bus16=1, bus8=1, io addrlines=10 00f2h 61h ls as n ranges number of address ranges = 2 address size = 2 length size = 1 00f4h f0h first i/o base address (lsb) first i/o base address = 1f0h 00f6h 01h first i/o base address (msb) 00f8h 07h first i/o length minus 1 first i/o range is 8 byte length 00fah f6h second i/o b ase address (lsb) second i/o base address = 3f6h 00fch 03h second i/o base address (msb) 00feh 01h second i/o length minus 1 second i/o range is 2 byte length 0100h eeh s p l m irq level share=1, pulse=1, level=1, mask=0, irq14 is recommended. 0102h 2 1h x rfu p ro a t power down, twin card supported. 0104h 1bh cistpl_cftable_entry configuration table entry tuple 0106h 05h tpl_link link to next tuple 0108h 02h i d configuration index no interface byte, non default entry, configuration index = 2 010a h 01h m ms ir io t p has vcc info 010ch 01h r di pi ai si hv lv nv nominal voltage only follows 010eh b5h x mantissa exponent vcc nominal is 3.3 volts 0110h 1eh extension
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 15 june . 2001 rev. 1.3 cis information(continued) offset data 7 6 5 4 3 2 1 0 description 0112h 1bh c istpl_cftable_entry configuration table entry tuple 0114h 0fh tpl_link link to next tuple 0116h c3h i d configuration index interface byte follows, default entry, configuration index = 3 0118h 41h w r p b interface type i/o interface; bvd's and wprot no t used; ready active and wait not used for memory cycles. 011ah 99h m ms ir io t p has vcc, i/o, irq and misc info 011ch 01h r di pi ai si hv lv nv nominal voltage only follows 011eh 55h x mantissa exponent vcc nominal is 5 volts 0120h eah r s e io add rlines i/o : range=1, bus16=1, bus8=1, io addrlines=10 0122h 61h ls as n ranges number of address ranges = 2 address size = 2 length size = 1 0124h 70h first i/o base address (lsb) first i/o base address = 170h 0126h 01h first i/o base address (msb) 0128h 07h first i/o length minus 1 first i/o range is 8 byte length 012ah 76h second i/o base address (lsb) second i/o base address = 376h 012ch 03h second i/o base address (msb) 012eh 01h second i/o length minus 1 second i/o range is 2 byte length 01 30h eeh s p l m irq level share=1, pulse=1, level=1, mask=0, irq14 is recommended. 0132h 21h x rfu p ro a t power down, twin card supported. 0134h 1bh cistpl_cftable_entry configuration table entry tuple 0136h 05h tpl_link link to next tuple 0138h 03h i d configuration index no interface byte, non default entry, configuration index = 3 013ah 01h m ms ir io t p has vcc info 013ch 01h r di pi ai si hv lv nv nominal voltage only follows 013eh b5h x mantissa exponent vcc nominal is 3.3 volts 0140h 1eh e xtension 0142h 14h cistpl_no_link no link tuple 0144h 00h tpl_link link to next tuple 0146h ffh cistpl_end end of list tuple
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 16 june . 2001 rev. 1.3 ata register specifications data register this register is a 16 bit register which is used to transfer data blocks betwe en the card data buffer and the host. data may be transferred by either a series of word accesses to the data register or a series of byte accesses to the data register. d15 d14 d13 d12 d11 d10 d9 d8 data word odd data byte d7 d6 d5 d4 d3 d2 d1 d0 da ta word data byte error register this register contains additional information about the source of an error which has occurred in processing of the preceding command. this register should be checked by the host when err bit in the status register is set . the error register is a read only register. d7 d6 d5 d4 d3 d2 d1 d0 bbk unc 0 idnf 0 abrt 0 amn f field function bbk this bit is set when a bad block is detected in requested id field. host can not read/write on data area that is marked as a bad bloc k. unc this bit is set when uncorrectable error is occurred at reading the card. idnf the requested sector id is in error or cannot be found. abrt this bit is set if the command has been aborted because of the card status condition. (not ready, write fa ult, etc.) or when an invalid command has been issued. amnf this bit is set in case of a general error. feature register this register is written by the host to provide command specific information to the drive regarding features of the drive which the host wish to utilize. the feature register is a write only register. d7 d6 d5 d4 d3 d2 d1 d0 feature byte sector count register this register is written by the host with the number of sectors or blocks to be processed in the subsequent command. after t he command is complete, the host may read this register to obtain the count of sectors left unprocessed by the command. d7 d6 d5 d4 d3 d2 d1 d0 sector count sector number register this register is written by the host with the starting sector number to be used in the subsequent cylinder - head - sector command. after the command is complete, the host may read the final sector number from this register. when logical block addressing is used, this register is written by the host with bit7 to 0 of the starting logical block number and contains bit7 to 0 of the final logical block number after the command is complete. d7 d6 d5 d4 d3 d2 d1 d0 sector number logical block number bits a07 - a00(lba addressing) cylinder low register this register is written by the host with the low - order byte of the starting cylinder address to be used in the subsequent cylinder - head - sector command. after the command is complete, the host may read the low - order byte of the final cylinder number from this register. when logical bloc k addressing is used, this register is written by the host with bits15 to 8 of the starting logical block number and contains bits15 to 8 of the final logical block number after the command complete. d7 d6 d5 d4 d3 d2 d1 d0 cylinder low byte logical blo ck number bits a15 - a08(lba addressing) cylinder high register this register is written by the host with the high - order byte of the starting cylinder address to be used in the subsequent cylinder - head - sector command. after the command is complete, the hos t may read the high - order byte of the final cylinder number from this register. when logical block addressing is used, this register is written by the host with bits 23 to 16 of the starting logical block number and contains bits23 to 16 of the final logic al block number after the command is complete. d7 d6 d5 d4 d3 d2 d1 d0 cylinder high byte logical block number bits a23 - a16(lba addressing)
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 17 june . 2001 rev. 1.3 drive/head register the drive/head register is used to specify the selected drive of a pair of drives sharing a set of registers. d7 d6 d5 d4 d3 d2 d1 d0 x lba x drv hs3 hs2 hs1 hs0 lba27 lba26 lba25 lba24 field function x undefined . ?0? or ?1?. lba this bit is ?0? for chs addressing and ?1? for logical block addressing. drv this bit is number of the drive which the host has selected. when drv is cleared, drive0 is selected. when drv is set, drive1 is selected. the card is selected to be drive0 or to be drive1 using the ?copy? field of the pc card socket copy register. hs3 - 0 lba27 - 24 hs3 - 0 of the head number in chs addressing or lba27 - 24 of the logical block number in lba addressing. status and alternate status registers the status register and the alternate status register return the card status when read by the host. reading the status register cle ars a pending interrupt request while reading the alternate status register does not. the status register and the alternate status register are read only registers. d7 d6 d5 d4 d3 d2 d1 d0 bsy drdy dwf dsc drq corr idx err field function bsy this bit is set when the card internal operation is executing. when this bit is set to ?1?, other bits in this register are invalid. drdy drdy indicates whether the card is capable of performing card operations. dwf this bit, if set, indicates a write fault has occurred. dsc this bit is set when the drive seek complete. drq this bit is set when the information can be transferred between the host and data register. corr this bit is set when a correctable data error has been occurred and the data has been correc ted. idx this bit is always set to ?0?. err this bit is set when the previous command has ended in some type of error. the error information is set in the other status register bits or error register. this bit is cleared by the next command. command re gister the command register contains the command code being sent to the device. command execution begins immediately after this register is written. the command register is a write only register. d7 d6 d5 d4 d3 d2 d1 d0 command device control register this register is used to control the card interrupt request and to issue a soft reset to the card. the device control register is a write only register. d7 d6 d5 d4 d3 d2 d1 d0 x x x x 1 srst nien 0 field function x don?t care. 1 this bit is set to ?1?. srst this bit is set to ?1? in order to force the card to perform a command block reset operation. this does not change the card configuration registers as a hardware reset does. the card remains in reset until this bit is reset to ?0?. nien this bi t is used for enabling ireq#. when this bit is set to ?0?, ireq# is enabled. when this bit is set to ?1?, ireq# is disabled. 0 this bit is set to ?0?. drive address register this register is provided for compatibility with the at disk drive interface. d7 d6 d5 d4 d3 d2 d1 d0 x nwt g nhs3 - 0 nds1 nds0 field function x this bit is unknown. nwtg this bit is set to ?0? when a flash write operation is in progress, otherwise it is set to ?1?. nhs3 - 0 these bits is the negative value of head select bits in drive/head register. nds1 this bit is set to ?0? when slave drive is act ive and selected. nds0 this bit is set to ?0? when master drive is active and selected.
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 18 june . 2001 rev. 1.3 ata command specifications this table summarizes the ata command set with the paragraphs. following shows the support commands and command codes which are written in command registers. command code fr sc sn cy dr hd check power mode 98h, e5h y execute drive diagnostic 90h y erase sector(s) c0h y y y y y format track 50h y y y y identify drive ech y idle 97h, e3h y y idle immediate 95h, e1h y initialize drive parameters 91h y y y read buffer e4h y read long sector 22h, 23h y y y y read multiple c4h y y y y y read sector(s) 20h, 21h y y y y y read verify sector(s) 40h, 41h y y y y y recalibrate 1xh y request sense 03h y seek 7xh y y y y set features efh y y y set multiple mode c6h y y set sleep mode 99h, e6h y standby 96h, e2h y standby immediate 94h, e0h y translate sector 87h y y y y y wear level f5h y write buffer e8h y write long sector 32h, 33h y y y y write multiple c5h y y y y y write multiple without erase cdh y y y y y write sector(s) 30h, 31h y y y y y write sector without erase 38h y y y y y write verify 3ch y y y y y fr : feature registe r, sc : sector count register, sn : sector number register, cy : cylinder low/high register, dr drive bit of drive/head register, hd : head no. of drive/head register,
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 19 june . 2001 rev. 1.3 check power mode(98h, e5h) this command checks the power mode. execute driv e diagnostic(90h) this command performs the internal diagnostic tests implemented by the card. erase sector(s)(c0h) this command is used to pre - erase and condition data sectors in advance of a write without erase or write multiple without erase command. format track(50h) this command writes the desired head and cylinder of the selected drive with a ffh pattern. identify drive(ech) this command enables the host to receive parameter information from the card. (refer to the identify drive information ta ble.) idle(97h, e3h) this command causes the card to set bsy, enter the idle mode, clear bsy and generate an interrupt. if the sector count is non - zero, the automatic power down mode is enabled. if the sector count is zero, the automatic power down mode is disabled. idle immediate(95h, e1h) this command causes the card to set bsy, enter the idle mode, clear bsy and generate an interrupt. initialize drive parameters(91h) this command allows the host to alter the number of sectors per track and the numb er of heads per cylinder. read buffer(e4h) this command enables the host to read the current contents of the card?s sector buffer. read long sector(22h, 23h) this command is similar to the read sector(s) command except the contents of the sector count register are ignored and only one sector is read. the 512 data bytes and 4 ecc bytes are read into the buffer(with no ecc correction) and then transferred to the host. read multiple(c4h) this command performs similarly to the read sector(s) command. inte rrupt are not generated on each sector, but on the transfer of a block which contains the number of sectors defined by a set multiple command. read sector(s)(20h, 21h) this command transfers data from the card to the host. data transfer starts at the sec tor specified by the cylinder, head, and sector number registers, and proceeds for the number of sectors specified in the sector count register. read verify sector(s)(40h, 41h) this command is identical to the read sector(s) command, except that drq is n ot asserted, and no data is transferred to the host. recalibrate(1xh) although this command is supported for backward compatibility, it has no actual function. the card will always return good status at the completion of this command. request sense(03 h) this command requests extended error information for the previous command. seek(7xh) this command is supported for backward compatibility. although this command has no actual function, it does perform a range check of valid track, and posts an idnf e rror if the head or cylinder specified are out of bounds. set features(efh) this command is used by the host to establish or select certain features. set multiple mode(c6h) this command enables the card to perform read and write multiple operations and establishes the block count for these commands. this card supports 1 sector block size. set sleep mode(99h, e6h) this command causes the card to set bsy, enter the sleep mode, clear bsy and generate an interrupt.
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 20 june . 2001 rev. 1.3 standby(96h, e2h) this command causes the card to set bsy, enter the standby mode, clear bsy and generate an interrupt. standby immediate(94h, e0h) this command causes the card to set bsy, enter the standby mode, clear bsy and generate an interrupt. translate sector(87h) this command allo ws the host to know the number of times an user sector has been erased and programmed. this card doesn't support the hot count value. wear leveling(f5h) although this command is supported for backward compatibility, it has no actual function. the card wi ll always return good status at the completion of this command. write buffer(e8h) this command enables the host to overwrite contents of the card?s sector buffer with any data pattern desired. this command has the same protocol as the write sector(s) com mand and transfers 512 bytes. write long sector(32h, 33h) this command is similar to the write sector(s) except the contents of the sector count register are ignored and only one sector is written. the 512 data bytes and 4 ecc bytes are transferred from the host and then written from the buffer to the flash. write multiple(c5h) this command is similar to the write sector(s) command. interrupts are not presented on each sector, but on the transfer of a block which contains the number of sectors defined b y set multiple command. write multiple without erase(cdh) this command is similar to the write multiple command. the sectors should be pre - erased with the erase sector command before this command is issued. if the sector is not pre - erased, write multiple command operation will occur. write sector(s)(30h, 31h) this command transfers data from the host to the card. data transfer starts at the sector specified by the cylinder, head, and sector number registers, and proceeds for the number of sectors s pecified in the sector count register. write sector without erase(cdh) this command is similar to the write sector(s) command. the sectors should be pre - erased with the erase sector command before this command is issued. if the sector is not pre - erased, write sector command operation will occur. write verify(3ch) this command is similar to the write sector(s) command, except each sector is verified immediately after being written.
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 21 june . 2001 rev. 1.3 identify drive information word address data description gene ral configuration bit - significant information 15 1 non - rotating disk drive 14 0 format speed tolerance gap not required 13 0 track offset option not available 12 0 data strobe offset option not available 11 0 rotational speed tolerance is < 0.5% 10 1 disk transfer rate > 10mbs 9 0 10mbs <= disk transfer rate > 5mbs 8 0 disk transfer rate <= 5mbs 7 1 removable cartridge drive 6 0 not a fixed drive 5 0 spindle motor control option not implemented 4 0 head switch time > 15us 3 1 not mfm encoded 2 0 not soft sectored 1 1 hard sectored 0 848ah 0 0 reserved 1 xxxxh number of cylinders 32mb:01e9, 64mb:03d2, 128mb:03d2, 192mb:02dd, 256mb:03d2, 320mb:026c, 384mb:02e9, 448mb:0365, 512mb:03e1 2 0000h reserved 3 00xxh number of heads ( 32mb:04, 64mb:04, 128mb:08, 192 - 256mb:10) 4 0000h number of unformatted bytes per track 5 0200h number of unformatted bytes per sector 6 00xxh number of sectors per track (32 ? 256mb:20, 320 ? 512mb:3f) 7 - 8 xxxxh, xxxxh number of sectors per ca rd (word 7 = msw, word 8 = lsw) 32mb:0000f480, 64mb:0001e900, 128mb:0003d200, 192mb:0005ba00, 256mb:0007a400, 320mb:00098940, 384mb:000b7570, 448mb:000d5db0, 512mb:000f45f0 9 0000h reserved 10 - 19 2020h reserved 20 0001h buffer type: single ported, singl e - sector, w/o read cache 21 0001h buffer size, in 512 byte increments 22 0004h ecc length used on read and write long command 23 - 26 xxxxh firmware revision, 8 ascii characters 27 - 46 xxxxh model number, 40 ascii characters. (32mb:mf0032m - 11at) 47 0001h maximum block count=1 for read/write multiple commands 48 0000h cannot perform doubleword i/o 49 0200h capabilities: lba supported, dma not supported 50 0000h reserved 51 0200h pio timing cycle timing mode 2 52 0000h dma transfer not supported 53 000 1h words 54 - 58 are valid 54 xxxxh number of current cylinders 55 xxxxh number of current heads 56 xxxxh number of current sectors per track 57 xxxxh lsw of the current capacity in sectors 58 xxxxh msw of the current capacity in sectors 59 010xh curre nt setting for block count for r/w multiple commands 60 xxxxh lsw of the total number of user addressable lba mode 61 xxxxh msw of the total number of user addressable lba mode 6 2 - 255 0000h reserved
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 22 june . 2001 rev. 1.3 absolute maximum ratings symbol parameter conditions ratings unit v cc supply voltage - 0.3~6.2 v v i input voltage - 0.3~v cc +0.3 v v o output voltage with respect to gnd - 0.3~v cc +0.3 v t opr operating temperature 0~ 7 0 c t stg storage temperature - 10~80 c recommended operating conditions limits symbol param eter min. typ. max. unit v cc (5v) v cc supply voltage 4.5 5.0 5.5 v v cc (3.3v) v cc supply voltage 3.135 3.3 3.465 v gnd system ground 0 v v ih high input voltage 0.7v cc v cc v v il low input voltage 0 0.8 v dc electrical characteristics (t a=0~ 7 0c, vcc=5v10% or vcc=3.3v5%, unless otherwise noted) limits min. typ. max. symbol parameter test condition 3.135v 4.5v 3.3v 5.0v 3.465v 5.5v unit i oh =3ma (3.135v) 4ma (4.5v) ready, i npack#, bvd1, bvd2 v oh high output voltage i oh =6ma (3.135v) 8ma (4.5v) the other outputs 0.8v cc - v i ol = - 3ma (3.135v) - 4ma (4.5v) ready, inpack#, bvd1, bvd2 v ol low output voltage i ol = - 6ma (3.135v) - 8ma (4.5v) the other outputs - 0.4 v i oz output current in off state ce1#=ce2#= v ih d15 - d0 - 10 a i ccr active supply current (read) output open 30 35 32mb 50 55 64mb 60 65 i ccw active supply current (write) 128 - 512mb 90 100 100 125 ma i ccs standby current (auto power down) reg# = ce1# = ce2# = vcc oe# = iord# = vcc we# = iowr# = vcc a0 - a10 = gnd 0.15 0.20 3.0 4.0 ma capacitance limits symbol parameter test condition min. typ. max. unit c i input capacitance v i =gnd, vi=25mvrms, f=1 mh z , ta=25c 45 pf c o out put capacitance v o =gnd, vo=25mvrms, f=1 mh z , ta=25c 45 note : these parameters are not 100% tested.
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 23 june . 2001 rev. 1.3 ac electrical characteristics memory timing read cycle[attribute] (ta=0~70c, vcc=5v10% or vcc=3.3v5% unless otherwise noted) limits symbol parameter min. typ. max. unit tcr read cycle time 300 ns ta(a) address access time 300 ns ta(ce) card enable access time 300 ns ta(oe) output enable access time 150 ns tdis(ce) output disable time (from ce) 100 ns tdis(oe) output disable time (from oe) 100 ns ten(ce) output enable time (from ce) 5 ns ten(oe) output enable time (from oe) 5 ns tv(a) data valid time (after address change) 0 ns read cycle[common] (ta=0~70c, vcc=5v10% or vcc=3.3v5% unless otherwise noted) limits symbo l parameter min. typ. max. unit tcr read cycle time 250 ns ta(a) address access time 250 ns ta(ce) card enable access time 250 ns ta(oe) output enable access time 125 ns tdis(ce) output disable time (from ce) 100 ns tdis(oe) outp ut disable time (from oe) 100 ns ten(ce) output enable time (from ce) 5 ns ten(oe) output enable time (from oe) 5 ns tv(a) data valid time after address change 0 ns
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 24 june . 2001 rev. 1.3 write cycle[ common] (ta=0~ 7 0c, vcc=5v10% or vcc=3.3v5% unl ess otherwise noted) limits symbol parameter min. typ. max. unit tcw write cycle time 250 ns tw(we) write pulse width 150 ns tsu(a) address setup time 30 ns tsu(a - weh) address setup time with respect to we high 180 ns tsu(ce - weh) card ena ble setup time with respect to we high 180 ns tsu(d - weh) data setup time with respect to we high 80 ns th(d) data hold time 30 ns trec(we) write recovery time 30 ns tdis(we) output disable time (from we) 100 ns tdis(oe) output disable time ( from oe) 100 ns ten(we) output enable time (from we) 5 ns ten(oe) output enable time (from oe) 5 ns tsu(oe - we) oe set up time with respect to we low 10 ns th(oe - we) oe hold time with respect to we high 10 ns
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 25 june . 2001 rev. 1.3 memory timing diagram read cyc le write cycle t cr t a (a) ta (ce) ten (ce) ten (oe) tdis (oe) t v(a) ta (oe) hi - z t dis(ce) an, reg# v ih dm (d out ) v oh v ol oe# v ih v il ce# v ih v il v il we# =?h? level note: indicates the don?t care input output valid dm (d out ) v oh v ol hi - z t en(oe) t cw t su(ce - weh) t su(a - weh) t su(a) th (oe - we) v ih v il an, reg# t w(we) t su(oe - we) ce# v ih v il t dis(oe) t dis(we) dm (d in ) v ih v il v il we# v ih oe# v ih v il t rec(we) t h(d) t su(d - weh) t en(we) data input stable hi - z
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 26 june . 2001 rev. 1.3 i/o read (input) timing limit symbol parameter min max unit td(iord) data delay after iord# 100 ns th(iord) data hold following iord# 0 ns tw(iord) iord# width time 165 ns t sua(iord) address setup before iord# 70 ns tha(iord) address hold following iord# 20 ns tsuce(iord) ce# setup before iord# 5 ns thce(iord) ce# hold following iord# 20 ns tsureg(iord) reg# setup before iord# 5 ns threg(iord) reg# hold following io rd# 0 ns tdfinpack(iord) inpack# delay falling from iord# 0 45 ns tdrinpack(iord) inpack# delay rising from iord# 45 ns tdfiois16(adr) iois16# delay falling from address 35 ns tdriois16(adr) iois16# delay rising from address 35 ns the maximum load on inpack# and iois16# are 1 lsttl with 50 pf total load. i/o write (output) timing limit symbol parameter min max unit tsu(iowr) data setup before iowr# 60 ns th(iowr) data hold following iowr# 30 ns tw(iowr) iowr# width time 165 ns tsua(iowr ) address setup before iowr# 70 ns tha(iowr) address hold following iowr# 20 ns tsuce(iowr) ce# setup before iowr# 5 ns thce(iowr) ce# hold following iowr# 20 ns tsureg(iowr) reg# setup before iowr# 5 ns threg(iowr) reg# hold following iowr# 0 n s tdfiois16(adr) iois16# delay falling from address 35 ns tdriois16(adr) iois16# delay rising from address 35 ns the maximum load on inpack# and iois16# are 1 lsttl with 50 pf total load.
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 27 june . 2001 rev. 1.3 i/o read (input) timing diagram t sureg(iord) t ha(iord) t hreg(iord) t suce(iord) t w(iord) t h ce(iord) t sua(iord) t drinpack(adr) t df inpack(iord) t driois16(adr) t d(iord) t dfiois16(adr) t h(iord) iois16# inpack# an reg# ce# iord# d[15::0]
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 28 june . 2001 rev. 1.3 i/o write (output) timing diagram t sureg(iowr) t ha(iowr) t hreg(iowr) t suce(iowr) t w(iowr) t hce(iowr) t su a(iowr) t driois16(adr) t su(iowr) t dfiois16(a dr) t h(iowr) iois16# an reg# ce# iowr# d[15::0]
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 29 june . 2001 rev. 1.3 ide ata timing (mode 2) ide ata i/o read (input) timing limit symbol parameter min max unit td(iord) data delay after iord# 50 ns th(iord) data hold following iord# 5 ns tw(iord) i ord# width time 70 ns tsua(iord) address setup before iord# 25 ns tha(iord) address hold following iord# 10 ns tsucs(iord) cs# setup before iord# 5 ns thcs(iord) cs# hold following iord# 10 ns tdfiocs16(adr) iocs16# delay falling from address 35 ns tdriocs16(adr) iocs16# delay rising from address 35 ns the maximum load on iocs16# are 1 lsttl with 50 pf total load. ide ata i/o write (output) timing limit symbol parameter min max unit tsu(iowr) data setup before iowr# 20 ns th(iowr) data hold following iowr# 10 ns tw(iowr) iowr# width time 70 ns tsua(iowr) address setup before iowr# 25 ns tha(iowr) address hold following iowr# 10 ns tsucs(iowr) cs# setup before iowr# 5 ns thcs(iowr) cs# hold following iowr# 10 ns tdfiocs16(adr ) iocs16# delay falling from address 35 ns tdriocs16(adr) iocs16# delay rising from address 35 ns the maximum load on iocs16# are 1 lsttl with 50 pf total load.
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 30 june . 2001 rev. 1.3 ide ata i/o read (input) timing diagram ide ata i/o write (out put) timing diagram t ha(iord) t sucs(iord) t w(iord) t hcs(iord) t sua(iord) t driocs16(adr) t d(iord) t dfiocs16(adr) t h(iord) iocs16# an cs# iord# d[15::0] tsucs(iowr) tw(iowr) thcs(iowr) tsua(iowr) tdriocs16(adr) tsu(iowr) tdf iocs16(adr) th(iowr) iocs16# an cs# iowr# d[15::0] tha(iowr)
mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 31 june . 2001 rev. 1.3 recommended power up/down conditions (ta=0~ 7 0c, unless otherwise noted) limits symbol parameter conditions min. typ. max. unit 0v vcc <2v 0 vcc v 2v vcc mitsubishi storage card preliminary mf0xxxx - 11 atxx series ata pc cards mitsubishi electric 32 june . 2001 rev. 1.3 these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customer?s application; they do not convey any license under an y intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third - party?s rights, originating in the u se of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents inform ation on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electri c corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubi shi semiconductor home page (http://www.mitsubishichips.com/) . when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a tota l system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. mitsubishi ele ctric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semicon ductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of m itsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese gov ernment and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. please contact mitsubishi electric c orporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein. notes regarding these materials circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safet y when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non - flammable material or (iii) prevention against any malfunction or mishap. keep safty first in your circuit designs!

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